(1) Field of the Invention
The present invention relates to split-gate memory cells used in flash EEPROMs (Electrically Erasable Programmable Read Only Memories), and in particular, to a method of forming a split-gate flash memory cell having multi-self-aligned structure.
(2) Description of the Related Art
One of the important drivers for increased performance in computers is the higher levels of integration of circuits. This is accomplished by miniaturizing or shrinking device sizes on a given chip. Tolerances play an important role in being able to shrink dimensions on a chip. Self-alignment of various components in a device can help reduce those tolerances and improve packing density of chips. As is known in the art, a split-gate flash memory cell normally has a floating gate, a control gate, source and drain regions, and none of them are usually self-aligned with respect to each other. That is, floating gate is not aligned to the cell isolation regions, nor to the common source line, nor to the control gate, or word line. This is primarily because of the poly oxide process employed in forming the floating gate. Consequently, it is difficult to shrink such a device. It is disclosed later in the embodiments of the present invention a method of forming a multi-self-aligned structure where the memory cell can be substantially reduced in size with the attendant improved packing density and performance.
A method of forming a conventional split-gate flash memory cell is shown in FIG. 1a where a layer of gate oxide (30) is thermally grown over substrate (10). Next, a first polysilicon layer (40) is formed followed by the deposition of nitride layer (50). A photoresist layer (60) is then spun over the substrate and then patterned with a floating gate pattern as shown in FIG. 1b, which in turn, is etched into the nitride layer (50) as shown in FIG. 1c. The photoresist layer, which is no longer needed, is removed. Next, the first polysilicon that is exposed in the pattern openings in the nitride layer is oxidized to form polyoxide (45) as shown in FIG. 1d. Subsequently, the nitride layer is removed where now polyoxide (45) serves as a hard mask to remove all the first polysilicon portions except those that are covered by the polyoxide (FIG. 1e). As is well known in the art, this is usually accomplished by main etch followed by over-etch. It is at this etching step that the corner edge (47) is usually rounded off, as seen in FIG. 1e, which is not desirable for achieving fast program erase speed described below. It will be shown later in the embodiments of this invention that by employing a "smiling effect", the sharpness of corner edge (47) can be improved such that charge transfer between substrate (10) and floating gate (40), and then the charge transfer between the floating gate and control gate, (60), is fast. The control gate is formed by depositing a second polysilicon layer over intergate layer (50), also known as interpoly, which separates the two polysilicon layers, namely, the floating polygate and the control polygate. The completed split-gate cell structure is shown in FIG. 1f.
Over the years, numerous improvements in the performance as well as in the size of memory devices have been made by varying the simple, basic one-transistor memory cell, which contains one transistor and one capacitor. The variations consist of different methods of forming capacitors, with single, double or triple layers of polysilicon, and different materials for the word and bit lines. In general, memory devices include electrically erasable and electrically programmable read-only memories (EEPROMs) of flash electrically erasable and electrically programmable read-only memories (flash EEPROMS). Many types of memory cells for EEPROMs or flash EEPROMs may have source and drains regions that are aligned to a floating gate or aligned to spacers. When the source and drain regions are aligned to the floating gate, a gate electrode for a select transistor is separate from the control gate electrode of the floating gate transistor. Separate select and control gates increase the size of the memory cell. If the source and drain regions are aligned to a spacer formed after the floating gate is formed, the floating gate typically does not overlie portions of the source and drain regions. Programming and erasing performance is degraded by the offset between the floating gate and source and drain regions.
FIG. 1g, which is an enlarged view of FIG. 1f, is a conventional flash-EEPROM cell where two MOS transistors share a common source (25). A top view is shown in FIG. 1h. FIG. 1g is a cross-sectional view of the cell taken at 1g--1g crossing active region (15) defined by passive filed oxide or isolation region (13). A top view of the shared common source line is referenced as (70) in FIG. 1h.
In the cross-sectional view 1g, the first doped region, (20), lies within the substrate. The second doped region, (25), also lies within substrate (10) and is spaced apart form the first doped region (20). Channel region (23) lies within substrate (10) and between first (20) and second (25) doped regions. Gate oxide layer (30) overlies substrate (10). Floating gate (40), to which there is no direct electrical connection, and which overlies substrate (10), is separated from substrate (10) by a thin layer of gate oxide (30) while control gate (60), to which there is direct electrical connection, is generally positioned over the floating gate with intergate oxide (50) therebetween.
To program the transistor shown in FIG. 1g, charge is transferred from substrate (10) through gate oxide (30) and is stored on floating gate (40) of the transistor. The amount of charge is set to one of two levels to indicate whether the cell has been programmed "on" of "off." "Reading" of the cell's state is accomplished by applying appropriate voltages to the cell source (25), Vs, drain (20), Vd, and to control gate (60), Vg, and then sensing the amount of charge on floating gate (40). To erase the contents of the cell, charges are removed from the floating gate by transferring them to the word line (control gate) through the gate oxide. The path of the charge transfer is shown by arrows (41) in FIG. 1g.
This programming and erasing of an EEPROM is accomplished electrically and in-circuit by using Fowler-Nordheim (FN) tunneling for erasing, and channel-hot electron (CHE) injection for programming, as is well known in the art. FN tunneling usually requires higher voltage than the CHE mechanism. It is common practice use FN tunneling for both write and erase for NAND type of cell architecture, while CHE programming and FN tunneling erasure is used for NOR circuits. The latter approach is shown in FIG. 1g. Thus, in the programming mode, source (25) is coupled to the floating gate through a high voltage which in turn creates a high electric field between floating gate (40) and control gate (60), thereby causing injection of CHEs from substrate (10) to floating gate (40) in FIG. 1g. In the erase mode, on the other hand, the control gate is impressed with a high voltage and electrons are injected from the floating gate to the control gate through the FN tunneling mechanism, usually aided by the poly tip of the floating gate.
In the conventional memory cell shown in FIG. 1g, word lines (not shown) are connected to control gate (60) of the MOS transistor, while the length of the MOS transistor itself is defined by the source (25) drain (20) n+ regions shown in the same Figure. As is well known by those skilled in the art, the transistor channel is defined by masking the n+ regions. However, the channel length of the transistor varies depending upon the alignment of the floating gate (40) with the source and drain regions. This introduces significant variations in cell performance from die to die and from wafer to wafer. Furthermore, the uncertainty in the final position of the n+ regions causes variations in the series resistance of the bit lines connected to those regions, and hence additional variation in the cell performance. The multi-self-aligned structure of the present invention resolves the uncertainty of the prior art.
Erasing and programming speed of a split gate flash memory cell is governed by the capacitive coupling between different parts of the cell. As it will be described more fully later, the programming and erasing of the cell is accomplished by transferring charges between polysilicon or poly parts comprising the floating gate, control gate and the source region in the device substrate. A faster erase speed is achieved if the coupling ratio between the control gate and the floating gate is low, which in turn, is attained by having a thinner floating gate as well as a sharper edge on the gate. With conventional methods of forming split gate cells, it is difficult to have low coupling ratio because of the relatively tall sidewalls of the floating gate. This is compensated to a large extent by forming a sharp edge or tip on the floating gate. On the other hand, higher programming speed is achieved if the coupling ratio between the floating gate and the source region is higher, which can be attained with a thinner floating gate. It is disclosed in the embodiments of the present invention a method of forming a split gate flash memory cell having a thin floating gate and a sharp poly tip in order to improve erasing and programming speed of the cell. The method involves the use of a nitride layer in place of the poly oxide that is conventionally employed in forming the floating gate, and also using to advantage a so-called "smiling effect" which is normally taught away.
In U.S. Pat. No. 5,879,992, Hsieh, et al., provide a method for forming a split-gate flash memory cell having a step poly supporting an interpoly oxide of varying thickness for the purposes of improving the over-all performance of the cell. Polyoxide is formed over portions of a first polysilicon layer which in turn is partially etched to form a step adjacent to the side-wall of a floating gate underlying the polyoxide. A spacer is next formed of a hot temperature oxide over the step poly. An interpoly oxynitride is then formed and control gate is patterned overlapping the floating gate with the intervening interpoly oxide. The step poly and the spacer thereon form proper distances between the control gate and the floating gate while keeping the distance between the poly tip and the control gate unchanged so that appropriate couplings between the control gate and the floating gate, and between the floating gate and the substrate are achieved, thus improving the over-all performance of the split-gate flash memory having a step poly.
In another U.S. Pat. No. 5,858,840, Hsieh, et al., propose a method for forming a short and sharp gate bird's beak in order to increase the erase speed of a split-gate flash memory cell. This is accomplished by implanting nitrogen ions in the first polysilicon layer of the cell and removing them from the area where the floating gate is to be formed. Then, when the polysilicon layer is oxidized to form polyoxide, the floating gate region without the nitrogen ions oxidizes faster than the surrounding area still having the nitrogen ions. Consequently, the bird's beak that is formed at the edges of the polyoxide assumes a sharper shape with smaller size than that is found in prior art. This results in an increase in the erase speed of the memory cell.
A different method of making a split-gate flash EEPROM cell is disclosed by Ahn in U.S. Pat. No. 5,652,161. The method prevents the degradation of the tunnel oxide film of the cell due to the band-to-band tunneling and the secondary hot carrier which are generated by a high electric field formed at the overlap region between the junction region and the gate electrode when programming and erasure operations are performed by a high voltage to the structure in which the tunneling region is separated from the channel with a thick insulation film.
Still another method of making a flash memory for multi-level logic is shown by Lin, et al., in U.S. Pat. No. 5,851,881. The memory device has a poly stacked gate transistor in series with a MONOS transistor. The method begins by forming a tunnel oxide layer on the surface of a semiconductor substrate. The substrate has a stacked gate channel area and a MONOS channel area in the active regions. A poly floating gate electrode is formed over the stacked gate channel region. An ONO layer having a memory nitride layer is formed over the floating gate and the tunnel oxide layer over the MONOS channel region. A control gate electrode is formed over the ONO layer spanning across the poly floating gate electrode and the MONOS channel region. Source/drain regions are formed in the substrate. A poly flash transistor and a MONOS flash transistor combine to form the 4 level logic memory cell of the invention.
Hong, on the other hand, discloses in U.S. Pat. No. 5,427,968 an electronically erasable and reprogrammable memory integrated circuit device having split-gate memory cell with separated tunneling. A silicon substrate having field oxide layers isolating component regions are processed to construct a memory cell in each of the isolated component region. Each of the memory cells includes a drain and source region formed in the silicon substrate, with a channel formed between the drain and source regions. Ring-shaped floating gate surrounds and covers the periphery of the channel and is isolated with the drain and source regions respectively by two thin tunneling oxide layers that are separated from each other. The two separated tunneling oxide layers constitute two separated tunneling regions. A control gate layer covers the ring-shaped floating gate and the portion of the channel that is not covered by the floating gate layer, and is separated from the floating gate by an isolation layer. A gate oxide layer is formed between the control gate layer and channel.
It will be apparent to those skilled in the art that prior art provides methods for partially improving the performance of memory devices through reshaping and reforming the poly tip, affecting the coupling ratios between the substrate and the floating gate, and between the floating gate and the control gate, and also by providing partial self-alignment between different parts, of the cell. It is disclosed later in the embodiments of the present invention a multi-self-aligned structure where all the parts, namely, the floating and control gates, and source and drain regions, are all aligned with respect to each other. This arrangement provides the maximum shrinkage of the cell that is possible. Furthermore, the method makes it possible, through the use of "smiling effect", to form a thin and sharp poly tip in the floating gate, thereby improving the coupling ratio, and hence the over-all performance of the split-gate flash memory device.